DigiTimes Media, a prominent player in supply chain channels, has refreshed its blog post titled “Tomorrow’s Headlines”. Based on information gathered from numerous industry sources, Apple is set to be the inaugural customer to utilize TSMC’s advanced 2nm process.
Given Apple’s dominant control over TSMC’s production capacity for the 3nm technology, this revelation is hardly unexpected. It has been reconfirmed via supply chain channels.
Apple will be granted preference for TSMC’s 2nm chip production capability shortly. TSMC anticipates commencing the production of 2nm chips by the latter part of 2025. The decrease in node size is proportional to the decrease in transistor size, allowing for a greater number of transistors to be integrated into the processor. This results in improved speed and power efficiency.
Apple’s iPhones and Macs released this year are equipped with 3-nanometer processors. The iPhone 15 Pro model features the A17 Pro chip, while the Mac utilizes the M3 series chips. Both of these chips are created using the 3-nanometer node, which represents an advancement from the preceding 5-nanometer node.
The transition from 5-nanometer technology to 3-nanometer technology results in a notable 20% increase in the iPhone’s GPU speed, a 10% increase in the CPU speed, a doubling in the speed of the neural engine, and equivalent enhancements for the Mac.
TSMC is constructing two additional facilities to cater to the demands of manufacturing 2-nanometer chips and is currently in the process of authorizing a third facility. TSMC often constructs new facilities in response to the requirement for increased production capacity to accommodate substantial chip orders. Currently, TSMC is engaged in a significant expansion effort for the development of 2-nanometer technology.
TSMC will employ GAAFETs (all-gate field effect transistors) with nanosheets instead of FinFETs in the shift to 2nm technology, resulting in a more intricate production process. GAAFET technology facilitates enhanced performance by achieving higher speeds through the utilization of smaller transistor dimensions and reduced operating voltages.